The use of run length limited (RLL) binary codes is prevalent in the data transmission and data recording arts for encoding an unconstrained set of binary data into a constrained set of codewords having a minimum distance (d) of "0"s between "1"s (or recording transitions) and a maximum distance (k) of "0"s between "1"s. Run length limited (d,k) codes of various types are utilized for data transmission and for magnetic and optical data recording. One example is a set of variable length codes described in coassigned U.S. Pat. No. 3,689,899, Franaszek, issued Sep. 5, 1972. Another example is described in coassigned U.S. Pat. No. 4,413,251, Adler et al., issued Nov. 1, 1983, of an encoder for generating a noiseless sliding block RLL (1,7) code, with a 2:3 rate. The 2:3 rate means that for each 2 input (source) binary bits, a codeword of 3 output (channel) binary bits is generated, each "1" binary bit of the codeword representing a bit clock time with a transition, and each "0" binary bit representing a bit clock time without a transition.
A data set will include a VFO pattern at a specific location (typically a header) and of a particular known transition frequency to synchronize the read clock (typically a phase locked loop or PLL) to the codeword bit frequency. The VFO pattern is typically a repetitive codeword pattern, but which is identifiable because of its location in a header.
A known sync pattern is typically also provided between the VFO pattern and any encoded data to allow the RLL decoder to align to the codeword boundaries and to the start location of the incoming encoded data.
If the PLL does not acheive complete phase lock, or if the RLL decoder does not align to the codeword boundaries on the incoming data (either of which may happen if a media defect is present), the RLL decoder will not be able to successfully decode incoming encoded data. But the PLL may complete phase lock in encoded data (if it begins close enough), and the RLL decoder can be aligned if a second RLL synchronization pattern occurs. A second or subsequent RLL synchronization pattern is typically called a resync pattern, or simply a resync. A resync is typically inserted within the data, for example, as illustrated by U.S. Pat. No. 5,451,943, Satomura, issued Sep. 15, 1995. The resync pattern allows the PLL to regain proper phase synchronization with the codewords without substantial loss of data. As pointed out by Satomura, the resync pattern must not be confused with data since the appearance of the data codewords having the same pattern as the resync are likely to be detected instead as a resync pattern and not decoded as data, resulting in the loss of data. Thus, Satomura proposed a Resync pattern for a variable length RLL (1,7) code inserted at specific locations in the code (e.g., at every 20 bytes of input data), which reduces the digital sum value of the encoded data and can be detected. One of the patterns is an "X01000000001" pattern, which exceeds the (k) constraint of the RLL code and cannot be confused with data.
When a sync pattern is not detected (missed) or detected erroneously in the wrong position (e.g., due to a defect), the exact bit position and alignment to RLL codeword boundaries is not known. Accordingly, there is also uncertainty as to the exact location where a resync may be positioned. If this uncertainty in position is as large as the resync, a typical situation which exists in most tape drives, a resync detector will necessarily have to look for the resync in encoded data. For this reason, it is important that the resync be distinct from data, so it should be outside the codeword space of the RLL code used to encode data. To put the resync outside the codeword space of the RLL code, many resyncs are designed to have either a single long string of "0"s which violates the (k) constraint of the code, or a sequence of long strings of "0"s which cannot be encoded naturally, either of which is known as an RLL violation. Resync detectors look for this RLL violation, which should not occur in normally encoded data (in the absence of noise or defects). A difficulty in peak detection channels is that the intersymbol interference of high frequency signals tends to shift the detection of any transition away from an adjacent transition and towards the no transition zone ("0"s). Thus, some detected transistions tend to be shifted into positions such that the detected bit stream may not be detected as a Resync pattern.